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| january 2000 1 ? 2000 actel corporation v3.0 radtolerant fpgas features general characteristics ? tested total ionizing dose (tid) survivability level ? no single event latch-up below a minimum let threshold of 80 mev-cm2/mg for all rt devices ? packages: 84-pin, 132-pin, 172-pin, 196-pin, and 256-pin ceramic quad flat pack ? offered as class b and e-flow (actel space level flow) ? qml certified devices ? 100% military temperature tested (C55c to +125c) high density and performance ? 4,000 to 20,000 logic equivalent gates ? 2,000 to 10,000 asic equivalent gates ? up to 85 mhz internal performance ? up to 60 mhz system performance ? up to 228 user i/os ? up to four fast, low-skew clock networks easy logic integration ? non-volatile, user programmable ? pin-compatible commercial devices available for prototyping ? highly predictable performance with 100% automatic place and route ? 100% resource utilization with 100% pin-locking ? secure programming technology prevents reverse engineering and design theft ? permanently programmed for operation on power-up ? unique in-system diagnostic and verification capability with silicon explorer general description actel builds the most reliable field programmable gate arrays (fpgas) in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (fits), corresponding to a useful life of more than 40 years. actel fpgas are production-proven, with more than five million devices shipped and more than one trillion antifuses manufactured. actel devices are fully tested prior to shipment, with an out-going defect level of only 122 ppm (further reliability data is available in the actel device reliability report at http://www.actel.com/hirel ). additionally, the programmable architecture of these devices offers high performance, design flexibility, and fast and inexpensive prototypingall without the expense of test vectors, nre charges, long lead times, and schedule and cost penalties for design refinements. product family profile device rt1020 rt1280a rt1425a rt1460a rt14100a capacity system gates logic gates asic equivalent gates pld equivalent gates ttl equivalent package 20-pin pal equivalent packages 6,000 4,000 2,000 5,000 50 20 24,000 16,000 8.000 20,000 200 80 7,500 5,000 2,500 6,250 60 25 18,000 12,000 6,000 15.000 150 60 30,000 20,000 10,000 25,000 250 100 logic modules s-modules c-modules 547 n/a 547 1,232 624 608 310 160 150 848 432 416 1,377 697 680 user i/os (maximum) 69 140 100 168 228 performance system speed (maximum) 20 mhz 40 mhz 60 mhz 60 mhz 60 mhz packages (by pin count) cqfp 84 172 132 196 256
2 device description the rt1020 device contains the same architecture as the a1020, a1020a, and a1020b devices. the architecture, a combinatorial logic module, is a logic structure that has 8 inputs and 1 output. the logic itself is comprised of a 4-input mux, as described in figure 3 on page 6 . in addition, since the rt1020 device contains the same number of gates and i/os and has the same operating voltage as its commercial equivalent (a1020b), an inexpensive commercial grade a1020b-cq84 device can be used during the prototype phase, and replaced by the rt1020 in the flight units. the rt1280a device uses the a1280a die from the act 2 family of fpgas. it utilizes a two-module architecture, consisting of combinatorial modules (c-modules) and sequential modules (s-modules) optimized for both combinatorial and sequential designs. based on actels patented channeled array architecture, the rt1280a has 8,000 asic-equivalent gates and 140 user i/os. the rt1280a device is fully pin- and function-compatible with the commercially-equivalent a1280a-cq172c device for easy and inexpensive prototyping. the rt1425a, rt1460a and rt14100a devices use the a1425a, a1460a and a14100a die, respectively. these devices are derived from the act 3 family of fpgas, which also utilize the two-module channeled array architecture, and offer faster performance than the rt1280a. these devices also have fully pin- and function-compatible commercially-equivalent devices for easy and inexpensive prototyping. the a1425a-cq132c is used for the rt1425a, the a1460a-cq196c is used for the rt1460a, and the a14100a-cq256c is used for the rt14100a. radiation survivability total dose results are summarized in two ways. first by the maximum total dose level that is reached when the parts fail to meet a device specification but remain functional. for actel fpgas, the parameter that exceeds the specification first is i cc , the standby supply current. second by the maximum total dose that is reached prior to the functional failure of the device. the rt devices have varying total dose radiation survivability. the ability of these devices to survive radiation effects is both device and lot dependent. the customer must evaluate and determine the applicability of these devices to their specific design and environmental requirements. typical results for the rt1020 device has shown ~100krads (si) for standby i cc and >100krads for functional failure. rt1280a device have shown results from 4 to 10krads (si) for standby i cc , and 7 to 18krads for functional failure. act 3 devices typical results have shown 10 to 28krads for i cc , and 20 to 77krads for functional failure. actel will provide total dose radiation testing along with the test data on each pedigreed lot that is available for sale. these reports are available on our website or you can contact your local sales representative to receive a copy. a listing of available lots and devices is also provided. these results are only provided for reference and for customer information. for a radiation performance summary, see radiation performance of actel products on the actel website at http://www.actel.com/hirel . this summary will also show single event upset (seu) and single event latch up (sel) testing that has been performed on actel fpgas. qml certification actel has achieved full qml certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with mil-prf-38535, the performance specification used by the department of defense for monolithic integrated circuits. qml certification is a good example of actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. many suppliers of microelectronics components have implemented qml as their primary worldwide business system. appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout qml products life cycles. disclaimer all radiation performance information is provided for information purposes only and is not guaranteed. the total dose effects are lot-dependent, and actel does not guarantee that future devices will continue to exhibit similar radiation characteristics. in addition, actual performance can vary widely due to a variety of factors, including but not limited to, characteristics of the orbit, radiation environment, proximity to satellite exterior, amount of inherent shielding from other sources within the satellite, and actual bare die variations. for these reasons, actel does not guarantee any level of radiation survivability, and it is solely the responsibility of the customer to determine whether the device will meet the requirements of the specific design. development tool support the radtolerant devices are fully supported by actels line of fpga development tools, including the actel desktop series and designer advantage tools. the actel desktop series is an integrated design environment for pcs that includes design entry, simulation, synthesis, and place and route tools. designer advantage is actels suite of fpga development 3 radtolerant fpgas point tools for pcs and workstations that includes the actgen macro builder, designer with directtime timing driven place and route and analysis tools, and device programming software. in addition, the radtolerant devices contain actionprobe circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a devices internal logic nodes without design iteration. the probe circuitry is accessed by silicon explorer, an easy to use integrated verification and logic analysis tool that can sample data at 100 mhz (asynchronous) or 66 mhz (synchronous). silicon explorer attaches to a pcs standard com port, turning the pc into a fully functional 18 channel logic analyzer. silicon explorer allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. radtolerant device ordering information application (temperature range) c= commercial (0 to +70c) m = military (C55 to +125c) b = mil-std-883 class b e = extended flow (space level) speed grade std = standard speed C1 = approximately 15% faster than standard package type cq = ceramic quad flat pack (cqfp) part number rt1020 = 4,000 gatesradtolerant act 1 rt1280a = 16,000 gatesradtolerant act 2 rt1425a = 5,000 gatesradtolerant act 3 rt1460a = 12,000 gatesradtolerant act 3 rt14100a = 20,000 gatesradtolerant act 3 a1020b = 4,000 gatesact 1 a1280a = 16,000 gatesact 2 a1425a = 5,000 gatesact 3 a1460a = 12,000 gatesact 3 a14100a = 20,000 gatesact 3 package lead count rt1280a cq 172 e C 4 product plan speed grade application std C1* c m b e act 1 rt1020 device 84-pin ceramic quad flat pack (cqfp) 4 44 a1020b device (prototyping use) 84-pin ceramic quad flat pack (cqfp) 44 444 act 2 rt1280a device 172-pin ceramic quad flat pack (cqfp) 44 44 a1280a device (prototyping use) 172-pin ceramic quad flat pack (cqfp) 44 444 act 3 rt1425a device 132-pin ceramic quad flat pack (cqfp) 44 44 a1425a device (prototyping use) 132-pin ceramic quad flat pack (cqfp) 44 444 rt1460a device 196-pin ceramic quad flat pack (cqfp) 44 44 a1460a device (prototyping use) 196-pin ceramic quad flat pack (cqfp) 44 444 rt14100a device 256-pin ceramic quad flat pack (cqfp) 44 44 a14100a device (prototyping use) 256-pin ceramic quad flat pack (cqfp) 44 444 contact your actel sales representative for product availability. applications: c = commercial availability: 4 = available *speed grade: C1 = approx. 15% faster than standard m = military = not planned b = mil-std-883 e = extended flow device resources logic modules gate array equivalent gates user i/os fpga device type cqfp 84-pin cqfp 132-pin cqfp 172-pin cqfp 196-pin cqfp 256-pin rt1020/a1020b 547 2,000 69 rt1280a/a1280a 1,232 8,000 140 rt1425a/a1425a 310 2,500 100 rt1460a/a1460a 848 6,000 168 rt14100a/a14100a 1,377 10,000 228 package definitions: cqfp = ceramic quad flat pack (contact your actel sales representative for product availability.) 5 radtolerant fpgas radtolerant architecture the actel architecture is composed of fine-grained logic modules that produce fast, efficient logic designs. all devices are composed of logic modules, routing resources, clock networks, and i/o modules which are the building blocks for fast logic designs. logic modules these radtolerant devices contain two types of logic modules, combinatorial (c-modules) and sequential (s-modules). rt1020 and a1020b devices contain only c-modules. the c-module, shown in figure 1 , implements the following function: y=!s1*!s0*d00+!s1*s0*d01+s1*!s0*d10+s1*s0*d11 where: s0=a0*b0 s1=a1+b1 the s-module, shown in figure 2 , is designed to implement high-speed sequential functions within a single logic module. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d-type flip-flop or a transparent latch. to increase flexibility, the s-module register can be by-passed so it implements purely combinatorial logic. flip-flops can also be created using two c-modules. the seu characteristics differ between an s-module flip-flop and a flip-flop created using two c-modules. for details see the design techniques for radhard field programmable gate arrays application note at http://www.actel.com/hirel . figure 1 ? c-module implementation d00 d00 d10 d11 s0 s1 y a0 b0 a1 b1 figure 2 ? s-module implementation d11 d01 d00 d10 y out s1 s0 up to 7-input function plus d-type flip-flop with clear d11 d01 d00 d10 y s1 s0 up to 7-input function plus latch y up to 4-input function plus latch with clear d11 d01 d00 d10 yout s1 s0 up to 8-input function (same as c-module) s d1 d0 clr dq out clr dq out gate dq gate 6 the rt1020 logic module the rt1020 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources ( figure 3 ). the logic module can implement the four basic logic functions (nand, and, or, and nor) in gates of two, three, or four inputs. each function may have many versions, with different combinations of active-low inputs. the logic module can also implement a variety of d-latches, exclusivity functions, and-ors, and or-ands. no dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. i/o modules i/o modules provide the interface between the device pins and the logic array. a variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the macro library guide for more information). i/o modules contain a tri-state buffer, and input and output latches that can be configured for input, output, or bi-directional pins ( figure 4 ). the radtolerant devices contain flexible i/o structures in that each output pin has a dedicated output enable control. the i/o module can be used to latch input and/or output data, providing a fast set-up time. in addition, the actel designer series software tools can build a d flip-flop, using a c-module, to register input and/or output signals. actels designer series development tools provide a design library of i/o macros. the i/o macro library provides macro functions that can implement all i/o configurations supported by the radtolerant fpgas. routing structure the radtolerant device architecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into segments. varying segment lengths allow over 90% of the circuit interconnects to be made with only two antifuse connections. segments can be joined together at the ends, using antifuses to increase their length up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are located between the rows of modules, and are composed of several routing tracks. the horizontal routing tracks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. any segment that spans more than one-third the row length is considered a long horizontal segment. a typical channel is shown in figure 5 on page 7 . non-dedicated horizontal routing tracks are used to route signal nets. dedicated routing tracks are used for the global clock networks, and for power and ground tie-off tracks. figure 3 ? rt1020 logic module figure 4 ? i/o module g/clk* qd en pa d * can be configured as a latch or d flip-flop from array to a r r ay (using c-module) g/clk* qd 7 radtolerant fpgas vertical routing another set of routing tracks run vertically through the module. there are three types of vertical tracks, input, output, and long, that can be divided into one or more segments. each segment in an input track is dedicated to the input of a particular module. each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. long vertical tracks contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 5 . antifuse structures an antifuse is a normally open structure as opposed to the normally closed fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly testable structures, as well as efficient programming algorithms. the structure is highly testable because there are no pre-existing connections, enabling temporary connections to be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed, as well as isolate individual circuit structures to be tested. this can be done both before and after programming. for example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. figure 5 ? routing structure vertical routing tracks antifuses logic segmented horizontal routing tr a c k s modules 8 actel mil-std-883 product flow step screen 883 method 883class b requirement 1. internal visual 2010, test condition b 100% 2. temperature cycling 1010, test condition c 100% 3. constant acceleration 2001, test condition d or e, y 1 , orientation only 100% 4. seal a. fine b. gross 1014 100% 100% 5. visual inspection 2009 100% 6. pre-burn-in electrical parameters in accordance with applicable actel device specification 100% 7. burn-in test 1015, condition d, 160 hours @ 125c or 80 hours @ 150c 100% 8. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 9. percent defective allowable 5% all lots 10. final electrical test a. static tests (1) 25c (subgroup 1, table i) (2) C55c and +125c (subgroups 2, 3, table i) b. functional tests (1) 25c (subgroup 7, table i) (2) C55c and +125c (subgroups 8a and 8b, table i) c. switching tests at 25c (subgroup 9, table i) in accordance with applicable actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 11. external visual 2009 100% note: when destructive physical analysis (dpa) is performed on class b devices, the step coverage requirement as specified in method 2018 must be waived. 9 radtolerant fpgas actel extended flow 1 notes: 1. actel offers the extended flow for customers that require additional screening beyond the requirements of mil-std-883, class b . actel is compliant to the requirements of mil-std-883, paragraph 1.2.1, and mil-i-38535, appendix a. actel is offering this extended flo w incorporating the majority of the screening procedures as outlined in method 5004 of mil-std-883 class s. the exceptions to met hod 5004 are shown in notes 2 and 3 below. 2. wafer lot acceptance is performed to method 5007; however, the step coverage requirement as specified in method 2018 must be waived. 3. method 5004 requires a 100 percent, non-destructive bond pull (method 2023). actel substitutes a destructive bond pull (method 2011), condition d on a sample basis only. step screen method requirement 1. wafer lot acceptance 2 5007 with step coverage waiver all lots 2. destructive in-line bond pull 3 2011, condition d sample 3. internal visual 2010, condition a 100% 4. serialization 100% 5. temperature cycling 1010, condition c 100% 6. constant acceleration 2001, condition d or e, y 1 orientation only 100% 7. particle impact noise detection 2020, condition a 100% 8. radiographic 2012 100% 9. pre-burn-in test in accordance with applicable actel device specification 100% 10. burn-in test 1015, condition d, 240 hours @ 125c minimum 100% 11. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 12. reverse bias burn-in 1015, condition c, 72 hours @ 150c minimum 100% 13. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 14. percent defective allowable (pda) calculation 5%, 3% functional parameters @ 25c all lots 15. final electrical test a. static tests (1) 25c (subgroup 1, table1) (2) C55c and +125c (subgroups 2, 3, table 1) b. functional tests (1) 25c (subgroup 7, table 15) (2) C55c and +125c (subgroups 8a and b, table 1) c. switching tests at 25c (subgroup 9, table 1) in accordance with actel applicable device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 100% 16. seal a. fine b. gross 1014 100% 17. external visual 2009 100% 10 absolute maximum ratings 1 free air temperature range notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices should not be operated outside the recommended operating conditions. 2. v pp = v cc , except during device programming. 3. v sv = v cc , except during device programming. 4. v ks = gnd , except during device programming. 5. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd C 0.5v, the internal protection diode will be forward-biased and can draw excessive current. recommended operating conditions notes: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. 2. all power supplies must be in the recommended operating range. for more information, refer to the power-up design considerations application note at http://www.actel.com/appnotes . electrical specifications notes: 1. actel devices can drive and receive either cmos or ttl signal levels. no assignment of i/os as ttl or cmos is required. 2. tested one output at a time, v cc = min. 3. not tested; for information only. 4. v out = 0v, f = 1 mhz symbol parameter limits units v cc dc supply voltage 2, 3, 4 C0.5 to +7.0 v v i input voltage C0.5 to v cc +0.5 v v o output voltage C0.5 to v cc +0.5 v i io i/o source sink current 5 20 ma t stg storage temperature C65 to +150 c parameter commercial military units temperature range 1 0 to +70 C55 to +125 c power supply tolerance 2 5 10 %v cc symbol parameter test condition commercial military units min. max. min. max. v oh 1, 2 high level output i oh = C4 ma (cmos) 3.7 v i oh = C6 ma (cmos) 3.84 v v ol 1, 2 low level output i ol = +6 ma (cmos) 0.33 0.4 v v ih high level input ttl inputs 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il low level input ttl inputs C0.3 0.8 C0.3 0.8 v i in input leakage v i = v cc or gnd C10 +10 C10 +10 a i oz 3-state output leakage v o = v cc or gnd C10 +10 C10 +10 a c io i/o capacitance 3, 4 10 10 pf i cc(s) standby v cc supply current v i = v cc or gnd, i o = 0 ma 2 20 ma i cc(d) dynamic v cc supply current see the power dissipation section on page 11 . 11 radtolerant fpgas package thermal characteristics the device junction to case thermal characteristic is q jc , and the junction to ambient air characteristic is q ja . the thermal characteristics for q ja are shown with two different air flow rates. maximum junction temperature is 150c. a sample calculation of the absolute maximum power dissipation allowed for a cqfp 172-pin package at military temperature is as follows: power dissipation general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc C v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, on design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in power dissipation lower than that of pals or plds. by integrating multiple pals or plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated below for commercial, worst-case conditions. the static power dissipated by ttl loads depends on the number of outputs driving high or low and on the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33v will generate 42 mw with all outputs driving low, and 140 mw with all outputs driving high. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency-dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totempole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by equation 1: power (uw) = c eq * v cc 2 * f (1) where: package type pin count q jc q ja still air q ja 300 ft/min units ceramic quad flat pack 84 132 172 196 256 7.8 7.2 6.8 6.4 6.2 40 35 25 23 20 30 25 20 15 10 c/w c/w c/w c/w c/w max. junction temp. (c) C max. military temp. q ja c/w () ------------------------------------------------------------------------------------------------------------------ 150c C 125c 25c/w ------------------------------------ 1 . 0 w == i cc v cc power 2 ma 5.25v 10.5 mw c eq = equivalent capacitance in pf v cc = power supply in volts (v) f = switching frequency in mhz 12 equivalent capacitance is calculated by measuring i cc active at a specified frequency and voltage for each circuit component of interest. measurements are made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. equivalent capacitance values are shown below. ceq values for actel fpgas to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piece-wise linear summation over all components. since the rt1280a and a1280a have two routed array clocks, the dedicated_clk and io_clk terms do not apply. for all other devices all terms apply. power = v cc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 + 0.5 * (s 1 * c eqcd * f s1 ) dedicated_clk + (s 2 * c eqci * f s2 ) io_clk ](2) where: rt1020 a1020b rt1280a a1280a rt1425a a1425a rt1460a a1460a rt14100a a14100a modules (c eqm ) 3.7 5.8 6.7 input buffers (c eqi ) 22.1 12.9 7.2 output buffers (c eqo ) 32.1 23.8 10.4 routed array clock buffer loads (c eqcr ) 4.6 3.9 1.6 dedicated clock buffer loads (c eqcd ) n/a n/a 0.7 i/o clock buffer loads (c eqci ) n/a n/a 0.9 m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock (not applicable for rt1020 or a1020b.) r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock (not applicable for rt1020 or a1020b.) s 1 = fixed number of clock loads on the dedicated array clock (not applicable for rt1020, a1020b, rt1280a, or a1280a.) s 2 = fixed number of clock loads on the dedicated i/o clock (not applicable for rt1020, a1020b, rt1280a, or a1280a.) c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c eqcd = equivalent capacitance of dedicated array clock in pf c eqci = equivalent capacitance of dedicated i/o clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz (not applicable for rt1020 or a1020b.) f s1 = average dedicated array clock rate in mhz (not applicable for rt1020, a1020b, rt1280a, or a1280a.) f s2 = average dedicated i/o clock rate in mhz (not applicable for rt1020, a1020b, rt1280a, or a1280a.) 13 radtolerant fpgas fixed capacitance values for actel fpgas (pf) fixed clock loads (s 1 /s 2 act 3 only) determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the guidelines in the table below are meant to represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation. rt1020, a1020b, rt1280a, a1280a rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a device type r 1 routed_clk1 r 2 routed_clk2 rt1020, a1020b 69 n/a rt1280a, a1280a 168 168 rt1425a, a1425a 75 75 rt1460a, a1460a 165 165 rt14100a, a14100a 195 195 device type s 1 clock loads on dedicated array clock s 2 clock loads on dedicated i/o clock rt1425a, a1425a 160 100 rt1460a, a1460a 432 168 rt14100a, a14100a 697 228 logic modules (m) = 80% of combinatorial modules input switching (n) = # inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 )= 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l )=35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n )= f/5 average output switching rate (f p )= f/10 average first routed array clock rate (f q1 ) =f average second routed array clock rate (f q2 ) =f/2 average dedicated array clock rate (f s1 ) =n/a average dedicated i/o clock rate (f s2 ) =n/a logic modules (m) = 80% of combinatorial modules input switching (n) = # inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 )= 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l )=35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n )= f/5 average output switching rate (f p )= f/10 average first routed array clock rate (f q1 ) =f/2 average second routed array clock rate (f q2 ) =f/2 average dedicated array clock rate (f s1 ) =f average dedicated i/o clock rate (f s2 ) =f 14 rt1020, a1020b timing model rt1280a, a1280a timing model* output delay input delay i/o module t inyl = 3.9 ns t ird2 = 1.8 ns logic module t pd1 = 3.6 ns i/o module t rd1 = 1.1 ns t dlh = 8.3 ns array clock f max = 55 mhz t rd4 = 3.9 ns t rd8 = 8.1 ns predicted routing delays t ckh = 6.9 ns fo = 128 t ird1 = 1.1 ns t ird4 = 3.9 ns t ird8 = 8.1 ns t co = 3.6 ns t enhz = 12.3 ns t rd2 = 1.8 ns internal delays *values shown for rt1280a C1 at worst-case military conditions. ? input module predicted routing delay. output delays internal delays input delays t inh = 2.5 ns t insu = 3.5 ns i/o module d q t ingl = 6.6 ns t inyl = 3.6 ns t ird2 = 7.2 ns ? combinatorial logic module t pd1 = 5.2 ns sequential logic module i/o module t rd1 = 2.4 ns t dlh = 14.0 ns i/o module array clocks f max = 73 mhz combin- atorial logic included in t sud d q d q t outh = 0.0 ns t outsu = 0.5 ns t glh = 12.4 ns t dlh = 14.0 ns t enhz = 9.8 ns t rd1 = 2.4 ns t co = 5.2 ns t sud = 0.5 ns t hd = 0.0 ns t rd4 = 5.1 ns t rd8 = 9.2 ns predicted routing delays t ckh = 13.3 ns g g fo = 32 t rd2 = 3.4 ns 15 radtolerant fpgas rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a timing model* *values shown for rt14100a C1 at worst-case military conditions. output delays internal delays input delays t inh = 0.0 ns t insu = 2.1 ns i/o clock i/o module d q t icky = 7.0 ns f iomax = 100 mhz t iny = 4.2 ns t ird2 = 1.9 ns combinatorial logic module t pd = 3.0 ns sequential logic module i/o module t rd1 = 1.3 ns t dhs = 9.2 ns i/o module array clock f hmax = 100 mhz combin- atorial logic included in t sud d q d q t outh = 1.2 ns t outsu = 1.2 ns t dhs = 9.2 ns t enzhs = 7.7 ns t rd1 = 1.3 ns t co = 3.0 ns t sud = 1.0 ns t hd = 0.6 ns t rd4 = 2.6 ns t rd8 = 4.2 ns predicted routing delays t hckh = 5.5 ns t iockh = 3.5 ns (pad-to-pad) t ckhs = 14.4 ns 16 parameter measurement output buffer delays ac test load input buffer delays combinatorial macro delays pa d to ac test loads (shown below) d e tribuff in v cc gnd 50% pa d v ol v oh 1.5v t dlh 50% 1.5v t dhl e v cc gnd 50% pa d v ol 1.5v t enzl 50% 10% t enlz e v cc gnd 50% pa d gnd v oh 1.5v t enzh 50% 90% t enhz v cc pad load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 50 pf to the output under test v cc gnd 50 pf to the output under test r to v cc for t plz /t pzl r to gnd for t phz /t pzh r = 1 k w pa d y inbuf pa d 3v 0v 1.5v y gnd v cc 50% t inyh 1.5v 50% t inyl pad s a b y s, a, or b y gnd v cc 50% t plh y gnd gnd v cc 50% 50% 50% v cc 50% 50% t phl t phl t plh 17 radtolerant fpgas sequential timing characteristics flip-flops and latches (rt1280a, a1280a) note: 1. d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge-triggered) d e clk clr pre y d 1 g, clk e q pre, clr t wclka t wasyn t hd t suena t sud t rs t a t co t hena 18 sequential timing characteristics (continued) flip-flops and latches (rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a) ) note: 1. d represents all data functions involving a, b, and s for multiplexed flip-flops. (positive edge-triggered) d e clk clr y d 1 g, clk e q clr t wclka t wasyn t hd t suena t sud t clr t a t co t hena 19 radtolerant fpgas sequential timing characteristics (continued) input buffer latches (r1280a, a1280a) output buffer latches (rt1280a, a1280a) g pad pad clk pa d g clk t inh clkbuf t insu t suext t hext ibdl d g t outsu t outh pa d obdlhs d g 20 rt1020, a1020b timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) std speed parameter description min. max. units logic module propagation delays t pd1 single module 3.6 ns t pd2 dual module macros 8.4 ns t co sequential clock to q 3.6 ns t go latch g to q 3.6 ns t rs flip-flop (latch) reset to q 3.6 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.1 ns t rd2 fo=2 routing delay 1.8 ns t rd3 fo=3 routing delay 2.6 ns t rd4 fo=4 routing delay 3.9 ns t rd8 fo=8 routing delay 8.1 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 6.9 ns t hd 3 flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 6.9 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 8.4 ns t wasyn flip-flop (latch) asynchronous pulse width 8.4 ns t a flip-flop clock input period 17.5 ns f max flip-flop (latch) clock frequency (fo = 128) 55 mhz input module propagation delays t inyh pad to y high 3.9 ns t inyl pad to y low 3.9 ns input module predicted routing delays 1, 3 t ird1 fo=1 routing delay 1.1 ns t ird2 fo=2 routing delay 1.8 ns t ird3 fo=3 routing delay 2.6 ns t ird4 fo=4 routing delay 3.9 ns t ird8 fo=8 routing delay 8.1 ns notes: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. set-up times assume fanout of 3. further testing information can be obtained from the directtime analyzer utility. 3. optimization techniques may further reduce delays by 0 to 4 ns. 4. the hold time for the dfme1a macro may be greater than 0 ns. use the designer series 3.0 (or later) timer to check the hold t ime for this macro. 21 radtolerant fpgas rt1020, a1020b timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) std speed parameter description min. max. units global clock network t ckh input low to high fo = 16 fo = 128 6.0 6.9 ns t ckl input high to low fo = 16 fo = 128 7.9 8.7 ns t pwh minimum pulse width high fo = 16 fo = 128 8.0 8.4 ns t pwl minimum pulse width low fo = 16 fo = 128 1.5 2.2 ns t cksw maximum skew fo = 16 fo = 128 1.5 2.3 ns t p minimum period fo = 16 fo = 128 16.3 17.5 ns f max maximum frequency fo = 16 fo = 128 60 50 mhz ttl output module timing 1 t dlh data to pad high 8.3 ns t dhl data to pad low 9.3 ns t enzh enable pad z to high 8.1 ns t enzl enable pad z to low 9.8 ns t enhz enable pad high to z 12.3 ns t enlz enable pad low to z 11.1 ns d tlh delta low to high 0.07 ns/pf d thl delta high to low 0.10 ns/pf cmos output module timing 1 t dlh data to pad high 9.8 ns t dhl data to pad low 7.9 ns t enzh enable pad z to high 7.4 ns t enzl enable pad z to low 10.2 ns t enhz enable pad high to z 12.3 ns t enlz enable pad low to z 11.1 ns d tlh delta low to high 0.13 ns/pf d thl delta high to low 0.07 ns/pf notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes . 22 rt1280a, a1280a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd1 single module 5.2 6.1 ns t co sequential clock-to-q 5.2 6.1 ns t go latch g-to-q 5.2 6.1 ns t rs flip-flop (latch) reset-to-q 5.2 6.1 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 2.4 2.8 ns t rd2 fo=2 routing delay 3.4 4.0 ns t rd3 fo=3 routing delay 4.2 4.9 ns t rd4 fo=4 routing delay 5.1 6.0 ns t rd8 fo=8 routing delay 9.2 10.8 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input set-up 0.5 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable set-up 1.3 1.3 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock active pulse width 7.4 8.6 ns t wasyn flip-flop (latch) asynchronous pulse width 7.4 8.6 ns t a flip-flop clock input period 16.4 22.1 ns t inh input buffer latch hold 2.5 2.5 ns t insu input buffer latch set-up 3.5 3.5 ns t outh output buffer latch hold 0.0 0.0 ns t outsu output buffer latch set-up 0.5 0.5 ns f max flip-flop (latch) clock frequency 60 41 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing parameters for sequential macros constructed from c-modules can be obtai ned from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with respect to the pad and the d input. external se t-up/hold timing parameters must account for delay from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time. 23 radtolerant fpgas rt1280a, a1280a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units input module propagation delays t inyh pad-to-y high 4.0 4.7 ns t inyl pad-to-y low 3.6 4.3 ns t ingh g-to-y high 6.9 8.1 ns t ingl g-to-y low 6.6 7.7 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 6.2 7.3 ns t ird2 fo=2 routing delay 7.2 8.4 ns t ird3 fo=3 routing delay 7.7 9.1 ns t ird4 fo=4 routing delay 8.9 10.5 ns t ird8 fo=8 routing delay 12.9 15.2 ns global clock network t ckh input low to high fo = 32 fo = 384 13.3 17.9 15.7 21.1 ns t ckl input high to low fo = 32 fo = 384 13.3 18.2 15.7 21.4 ns t pwh minimum pulse width high fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t pwl minimum pulse width low fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t cksw maximum skew fo = 32 fo = 384 0.6 3.1 0.6 3.1 ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 8.6 13.8 8.6 13.8 ns t p minimum period fo = 32 fo = 384 13.7 16.0 16.2 18.9 ns f max maximum frequency fo = 32 fo = 384 73 63 62 53 mhz note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduc e delays by 0 to 4 ns. 24 rt1280a, a1280a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 11.0 13.0 ns t dhl data-to-pad low 13.9 16.4 ns t enzh enable-to-pad z to high 12.3 14.4 ns t enzl enable-to-pad z to low 16.1 19.0 ns t enhz enable-to-pad high to z 9.8 11.5 ns t enlz enable-to-pad low to z 11.5 13.6 ns t glh g-to-pad high 12.4 14.6 ns t ghl g-to-pad low 15.5 18.2 ns d tlh delta low to high 0.09 0.11 ns/pf d thl delta high to low 0.17 0.20 ns/pf cmos output module timing 1 t dlh data-to-pad high 14.0 16.5 ns t dhl data-to-pad low 11.7 13.7 ns t enzh enable-to-pad z to high 12.3 14.4 ns t enzl enable-to-pad z to low 16.1 19.0 ns t enhz enable-to-pad high to z 9.8 11.5 ns t enlz enable-to-pad low to z 11.5 13.6 ns t glh g-to-pad high 12.4 14.6 ns t ghl g-to-pad low 15.5 18.2 ns d tlh delta low to high 0.17 0.20 ns/pf d thl delta high to low 0.12 0.15 ns/pf notes: 1. delays based on 50 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes . 25 radtolerant fpgas rt1425a, a1425a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 3.8 4.4 ns t wclka flip-flop clock pulse width 3.8 4.4 ns t a flip-flop clock input period 7.9 9.3 ns f max flip-flop clock frequency 125 100 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns. 26 rt1425a, a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 9.9 11.6 ns t ckhs ioclk pad to pad h/l, high slew 10.5 11.6 ns t ckls ioclk pad to pad h/l, low slew 15.7 17.4 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading. 27 radtolerant fpgas rt1425a, a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 10.5 11.6 ns t ckhs ioclk pad to pad h/l, high slew 12.5 13.7 ns t ckls ioclk pad to pad h/l, low slew 18.1 20.1 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.0 3.5 ns t iopwh minimum pulse width high 3.9 4.4 ns t iopwl minimum pulse width low 3.9 4.4 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.5 0.5 ns t iop minimum period 7.9 9.3 ns f iomax maximum frequency 125 100 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 4.6 5.3 ns t hckl input high to low (pad to s-module input) 4.6 5.3 ns t hpwh minimum pulse width high 3.9 4.4 ns t hpwl minimum pulse width low 3.9 4.4 ns t hcksw maximum skew 0.4 0.4 ns t hp minimum period 7.9 9.3 ns f hmax maximum frequency 125 100 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes . 28 rt1425a, a1425a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=64) 5.5 6.4 ns t rckl input high to low (fo=64) 6.0 7.0 ns t rpwh min. pulse width high (fo=64) 4.9 5.7 ns t rpwl min. pulse width low (fo=64) 4.9 5.7 ns t rcksw maximum skew (fo=128) 1.1 1.2 ns t rp minimum period (fo=64) 10.1 11.6 ns f rmax maximum frequency (fo=64) 100 85 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 3.0 0.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns 29 radtolerant fpgas rt1460a, a1460a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns predicted input routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns. 30 rt1460a, a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 11.5 13.5 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 11.6 13.4 ns t ckls ioclk pad to pad h/l, low slew 17.8 19.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading. 31 radtolerant fpgas rt1460a, a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 10.9 12.8 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 14.1 16.0 ns t ckls ioclk pad to pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes . 32 rt1460a, a1460a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns 33 radtolerant fpgas rt14100a, a14100a timing characteristics (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock-to-q 3.0 3.5 ns t clr asynchronous clear-to-q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input set-up 1.0 1.0 ns t hd flip-flop (latch) data input hold 0.6 0.6 ns t suena flip-flop (latch) enable set-up 1.0 1.0 ns t hena flip-flop (latch) enable hold 0.6 0.6 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad-to-y 4.2 4.9 ns t icky input reg ioclk pad-to-y 7.0 8.2 ns t ocky output reg ioclk pad-to-y 7.0 8.2 ns t iclry input asynchronous clear-to-y 7.0 8.2 ns t oclry output asynchronous clear-to-y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may further reduce delays by 0 to 4 ns. 34 rt14100a, a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c ) C1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input flip-flop data hold 0.0 0.0 ns t insu input flip-flop data set-up 2.1 2.4 ns t ideh input data enable hold 0.0 0.0 ns t idesu input data enable set-up 8.7 10.0 ns t outh output flip-flop data hold 1.2 1.2 ns t outsu output flip-flop data set-up 1.2 1.2 ns t odeh output data enable hold 0.6 0.6 ns t odesu output data enable set-up 2.4 2.4 ns ttl output module timing 1 t dhs data-to-pad, high slew 7.5 8.9 ns t dls data-to-pad, low slew 11.9 14.0 ns t enzhs enable-to-pad, z to h/l, high slew 6.0 7.0 ns t enzls enable-to-pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable-to-pad, h/l to z, high slew 11.9 14.0 ns t enlsz enable-to-pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad-to-pad h/l, high slew 12.2 14.0 ns t ckls ioclk pad-to-pad h/l, low slew 17.8 17.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf note: 1. delays based on 35 pf loading. 35 radtolerant fpgas rt14100a, a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units cmos output module timing 1 t dhs data-to-pad, high slew 9.2 10.8 ns t dls data-to-pad, low slew 17.3 20.3 ns t enzhs enable-to-pad, z to h/l, high slew 7.7 9.1 ns t enzls enable-to-pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable-to-pad, h/l to z, high slew 11.6 14.0 ns t enlsz enable-to-pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad-to-pad h/l, high slew 14.4 16.0 ns t ckls ioclk pad-to-pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz notes: 1. delays based on 35 pf loading. 2. sso information can be found the simultaneously switching output limits for actel fpgas application note at http://www.actel.com/appnotes . 36 rt14100a, a14100a timing characteristics (continued) (worst-case military conditions, v cc = 4.5v, t j = 125c) C1 speed std speed parameter description min. max. min. max. units routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.5 0.0 3.5 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns 37 radtolerant fpgas pin description clk clock (input) rt1020 and a1020b only. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clka clock a (input) not applicable for rt1020 and a1020b. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) not applicable for rt1020 and a1020b. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground low supply voltage. hclk dedicated (hard-wired) array clock (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl clock input for sequential modules. this input is directly wired to each s-module, offering clock speeds independent of the number of s-modules being driven. this pin can also be used as an i/o. i/o input/output (input, output) i/o pin functions as an input, output, tri-state, or bi-directional buffer. input and output levels are compatible with standard ttl and cmos specifications. in the rt1020, a1020b, rt1280, and a1280a devices, unused i/o pins are automatically driven low. in the rt1425, a1425a, rt1460, a1460a, rt14100, and a14100a devices, unused i/o pins are automatically tri-stated. ioclk dedicated (hard-wired) i/o clock (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl clock input for i/o modules. this input is directly wired to each i/o module, offering clock speeds independent of the number of i/o modules being driven. this pin can also be used as an i/o. iopcl dedicated (hard-wired) i/o preset/clear (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl input for i/o preset or clear. this global input is directly wired to the preset and clear inputs of all i/o registers. this pin functions as an i/o when no i/o preset or clear macros are used. mode mode (input) the mode pin controls the use of diagnostic pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide debugging capability, the mode pin should be terminated to gnd through a 10 k w resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra, i/o probe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when verification has been completed. the pins probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb, i/o probe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when verification has been completed. the pins probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. v cc 5.0v supply voltage high supply voltage. 38 package pin assignments 84-pin cqfp (top view) pin #1 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 84-pin cqfp 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 39 radtolerant fpgas 84-pin cqfp pin number a1020b function rt1020 function pin number a1020b function rt1020 function 1 nc nc 43 i/o i/o 2 i/o i/o 44 i/o i/o 3 i/o i/o 45 i/o i/o 4 i/o i/o 46 i/o i/o 5 i/o i/o 47 i/o i/o 6 i/o i/o 48 i/o i/o 7 gnd gnd 49 gnd gnd 8 gnd gnd 50 gnd gnd 9 i/o i/o 51 i/o i/o 10 i/o i/o 52 i/o i/o 11 i/o i/o 53 clka, i/o clka, i/o 12 i/o i/o 54 i/o i/o 13 i/o i/o 55 mode mode 14 v cc v cc 56 v cc v cc 15 v cc v cc 57 v cc v cc 16 i/o i/o 58 i/o i/o 17 i/o i/o 59 i/o i/o 18 i/o i/o 60 i/o i/o 19 i/o i/o 61 sdi, i/o sdi, i/o 20 i/o i/o 62 dclk, i/o dclk, i/o 21 i/o i/o 63 pra, i/o pra, i/o 22 v cc v cc 64 prb, i/o prb, i/o 23 i/o i/o 65 i/o i/o 24 i/o i/o 66 i/o i/o 25 i/o i/o 67 i/o i/o 26 i/o i/o 68 i/o i/o 27 i/o i/o 69 i/o i/o 28 i/o i/o 70 i/o i/o 29 gnd gnd 71 gnd gnd 30 i/o i/o 72 i/o i/o 31 i/o i/o 73 i/o i/o 32 i/o i/o 74 i/o i/o 33 i/o i/o 75 i/o i/o 34 i/o i/o 76 i/o i/o 35 v cc v cc 77 v cc v cc 36 i/o i/o 78 i/o i/o 37 i/o i/o 79 i/o i/o 38 i/o i/o 80 i/o i/o 39 i/o i/o 81 i/o i/o 40 i/o i/o 82 i/o i/o 41 i/o i/o 83 i/o i/o 42 i/o i/o 84 i/o i/o 40 package pin assignments (continued) 132-pin cqfp (top view) 132-pin cqfp pin #1 index 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 92 93 94 95 96 97 98 99 33 32 31 30 29 28 27 26 25 8 7 6 5 4 3 2 1 41 radtolerant fpgas 132-pin cqfp pin number a1425a function rt1425a function pin number a1425a function rt1425a function pin number a1425a function rt1425a function 1 nc nc 45 i/o i/o 89 v cc v cc 2 gnd gnd 46 i/o i/o 90 gnd gnd 3 sdi, i/o sdi, i/o 47 i/o i/o 91 v cc v cc 4 i/o i/o 48 prb, i/o prb, i/o 92 gnd gnd 5 i/o i/o 49 i/o i/o 93 i/o i/o 6 i/o i/o 50 hclk, i/o hclk, i/o 94 i/o i/o 7 i/o i/o 51 i/o i/o 95 i/o i/o 8 i/o i/o 52 i/o i/o 96 i/o i/o 9 mode mode 53 i/o i/o 97 i/o i/o 10 gnd gnd 54 i/o i/o 98 ioclk, i/o ioclk, i/o 11 v cc v cc 55 i/o i/o 99 nc nc 12 i/o i/o 56 i/o i/o 100 nc nc 13 i/o i/o 57 i/o i/o 101 gnd gnd 14 i/o i/o 58 gnd gnd 102 i/o i/o 15 i/o i/o 59 v cc v cc 103 i/o i/o 16 i/o i/o 60 i/o i/o 104 i/o i/o 17 i/o i/o 61 i/o i/o 105 i/o i/o 18 i/o i/o 62 i/o i/o 106 gnd gnd 19 i/o i/o 63 i/o i/o 107 v cc v cc 20 i/o i/o 64 iopcl, i/o iopcl, i/o 108 i/o i/o 21 i/o i/o 65 gnd gnd 109 i/o i/o 22 v cc v cc 66 nc nc 110 i/o i/o 23 i/o i/o 67 nc nc 111 i/o i/o 24 i/o i/o 68 i/o i/o 112 i/o i/o 25 i/o i/o 69 i/o i/o 113 i/o i/o 26 gnd gnd 70 i/o i/o 114 i/o i/o 27 v cc v cc 71 i/o i/o 115 i/o i/o 28 i/o i/o 72 i/o i/o 116 clka, i/o clka, i/o 29 i/o i/o 73 i/o i/o 117 clkb, i/o clkb, i/o 30 i/o i/o 74 gnd gnd 118 pra, i/o pra, i/o 31 i/o i/o 75 v cc v cc 119 i/o i/o 32 i/o i/o 76 i/o i/o 120 i/o i/o 33 i/o i/o 77 i/o i/o 121 i/o i/o 34 nc nc 78 v cc v cc 122 gnd gnd 35 i/o i/o 79 i/o i/o 123 v cc v cc 36 gnd gnd 80 i/o i/o 124 i/o i/o 37 i/o i/o 81 i/o i/o 125 i/o i/o 38 i/o i/o 82 i/o i/o 126 i/o i/o 39 i/o i/o 83 i/o i/o 127 i/o i/o 40 i/o i/o 84 i/o i/o 128 i/o i/o 41 i/o i/o 85 i/o i/o 129 i/o i/o 42 gnd gnd 86 i/o i/o 130 i/o i/o 43 v cc v cc 87 i/o i/o 131 dclk, i/o dclk, i/o 44 i/o i/o 88 i/o i/o 132 nc nc 42 package pin assignments (continued) 172-pin cqfp (top view) 172-pin cqfp pin #1 index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 122 123 124 125 126 127 128 129 43 42 41 40 39 38 37 36 35 8 7 6 5 4 3 2 1 43 radtolerant fpgas 172-pin cqfp pin number a1280a function rt1280a function pin number a1280a function rt1280a function 1 mode mode 45 i/o i/o 2 i/o i/o 46 i/o i/o 3 i/o i/o 47 i/o i/o 4 i/o i/o 48 i/o i/o 5 i/o i/o 49 i/o i/o 6 i/o i/o 50 v cc v cc 7 gnd gnd 51 i/o i/o 8 i/o i/o 52 i/o i/o 9 i/o i/o 53 i/o i/o 10 i/o i/o 54 i/o i/o 11 i/o i/o 55 gnd gnd 12 v cc v cc 56 i/o i/o 13 i/o i/o 57 i/o i/o 14 i/o i/o 58 i/o i/o 15 i/o i/o 59 i/o i/o 16 i/o i/o 60 i/o i/o 17 gnd gnd 61 i/o i/o 18 i/o i/o 62 i/o i/o 19 i/o i/o 63 i/o i/o 20 i/o i/o 64 i/o i/o 21 i/o i/o 65 gnd gnd 22 gnd gnd 66 v cc v cc 23 v cc v cc 67 i/o i/o 24 v cc v cc 68 i/o i/o 25 i/o i/o 69 i/o i/o 26 i/o i/o 70 i/o i/o 27 v cc v cc 71 i/o i/o 28 i/o i/o 72 i/o i/o 29 i/o i/o 73 i/o i/o 30 i/o i/o 74 i/o i/o 31 i/o i/o 75 gnd gnd 32 gnd gnd 76 i/o i/o 33 i/o i/o 77 i/o i/o 34 i/o i/o 78 i/o i/o 35 i/o i/o 79 i/o i/o 36 i/o i/o 80 v cc v cc 37 gnd gnd 81 i/o i/o 38 i/o i/o 82 i/o i/o 39 i/o i/o 83 i/o i/o 40 i/o i/o 84 i/o i/o 41 i/o i/o 85 i/o i/o 42 i/o i/o 86 i/o i/o 43 i/o i/o 87 i/o i/o 44 i/o i/o 88 i/o i/o 44 89 i/o i/o 131 sdi, i/o sdi, i/o 90 i/o i/o 132 i/o i/o 91 i/o i/o 133 i/o i/o 92 i/o i/o 134 i/o i/o 93 i/o i/o 135 i/o i/o 94 i/o i/o 136 v cc v cc 95 i/o i/o 137 i/o i/o 96 i/o i/o 138 i/o i/o 97 i/o i/o 139 i/o i/o 98 gnd gnd 140 i/o i/o 99 i/o i/o 141 gnd gnd 100 i/o i/o 142 i/o i/o 101 i/o i/o 143 i/o i/o 102 i/o i/o 144 i/o i/o 103 gnd gnd 145 i/o i/o 104 i/o i/o 146 i/o i/o 105 i/o i/o 147 i/o i/o 106 gnd gnd 148 pra, i/o pra, i/o 107 v cc v cc 149 i/o i/o 108 gnd gnd 150 clka, i/o clka, i/o 109 v cc v cc 151 v cc v cc 110 v cc v cc 152 gnd gnd 111 i/o i/o 153 i/o i/o 112 i/o i/o 154 clkb, i/o clkb, i/o 113 v cc v cc 155 i/o i/o 114 i/o i/o 156 prb, i/o prb, i/o 115 i/o i/o 157 i/o i/o 116 i/o i/o 158 i/o i/o 117 i/o i/o 159 i/o i/o 118 gnd gnd 160 i/o i/o 119 i/o i/o 161 gnd gnd 120 i/o i/o 162 i/o i/o 121 i/o i/o 163 i/o i/o 122 i/o i/o 164 i/o i/o 123 gnd gnd 165 i/o i/o 124 i/o i/o 166 v cc v cc 125 i/o i/o 167 i/o i/o 126 i/o i/o 168 i/o i/o 127 i/o i/o 169 i/o i/o 128 i/o i/o 170 i/o i/o 129 i/o i/o 171 dclk, i/o dclk, i/o 130 i/o i/o 172 i/o i/o 172-pin cqfp (continued) pin number a1280a function rt1280a function pin number a1280a function rt1280a function 45 radtolerant fpgas package pin assignments (continued) 196-pin cqfp (top view) 196-pin cqfp pin #1 index 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 140 141 142 143 144 145 146 147 49 48 47 46 45 44 43 42 41 8 7 6 5 4 3 2 1 46 196-pin cqfp pin number a1460a function rt1460a function pin number a1460a function rt1460a function pin number a1460a function rt1460a function 1 gnd gnd 44 i/o i/o 87 i/o i/o 2 sdi, i/o sdi, i/o 45 i/o i/o 88 i/o i/o 3 i/o i/o 46 i/o i/o 89 i/o i/o 4 i/o i/o 47 i/o i/o 90 i/o i/o 5 i/o i/o 48 i/o i/o 91 i/o i/o 6 i/o i/o 49 i/o i/o 92 i/o i/o 7 i/o i/o 50 i/o i/o 93 i/o i/o 8 i/o i/o 51 gnd gnd 94 v cc v cc 9 i/o i/o 52 gnd gnd 95 i/o i/o 10 i/o i/o 53 i/o i/o 96 i/o i/o 11 mode mode 54 i/o i/o 97 i/o i/o 12 v cc v cc 55 i/o i/o 98 gnd gnd 13 gnd gnd 56 i/o i/o 99 i/o i/o 14 i/o i/o 57 i/o i/o 100 iopcl, i/o iopcl, i/o 15 i/o i/o 58 i/o i/o 101 gnd gnd 16 i/o i/o 59 v cc v cc 102 i/o i/o 17 i/o i/o 60 i/o i/o 103 i/o i/o 18 i/o i/o 61 i/o i/o 104 i/o i/o 19 i/o i/o 62 i/o i/o 105 i/o i/o 20 i/o i/o 63 i/o i/o 106 i/o i/o 21 i/o i/o 64 gnd gnd 107 i/o i/o 22 i/o i/o 65 i/o i/o 108 i/o i/o 23 i/o i/o 66 i/o i/o 109 i/o i/o 24 i/o i/o 67 i/o i/o 110 v cc v cc 25 i/o i/o 68 i/o i/o 111 v cc v cc 26 i/o i/o 69 i/o i/o 112 gnd gnd 27 i/o i/o 70 i/o i/o 113 i/o i/o 28 i/o i/o 71 i/o i/o 114 i/o i/o 29 i/o i/o 72 i/o i/o 115 i/o i/o 30 i/o i/o 73 i/o i/o 116 i/o i/o 31 i/o i/o 74 i/o i/o 117 i/o i/o 32 i/o i/o 75 prb, i/o prb, i/o 118 i/o i/o 33 i/o i/o 76 i/o i/o 119 i/o i/o 34 i/o i/o 77 hclk, i/o hclk, i/o 120 i/o i/o 35 i/o i/o 78 i/o i/o 121 i/o i/o 36 i/o i/o 79 i/o i/o 122 i/o i/o 37 gnd gnd 80 i/o i/o 123 i/o i/o 38 v cc v cc 81 i/o i/o 124 i/o i/o 39 v cc v cc 82 i/o i/o 125 i/o i/o 40 i/o i/o 83 i/o i/o 126 i/o i/o 41 i/o i/o 84 i/o i/o 127 i/o i/o 42 i/o i/o 85 i/o i/o 128 i/o i/o 43 i/o i/o 86 gnd gnd 129 i/o i/o 47 radtolerant fpgas 130 i/o i/o 153 i/o i/o 176 i/o i/o 131 i/o i/o 154 i/o i/o 177 i/o i/o 132 i/o i/o 155 v cc v cc 178 i/o i/o 133 i/o i/o 156 i/o i/o 179 i/o i/o 134 i/o i/o 157 i/o i/o 180 i/o i/o 135 i/o i/o 158 i/o i/o 181 i/o i/o 136 i/o i/o 159 i/o i/o 182 i/o i/o 137 v cc v cc 160 i/o i/o 183 gnd gnd 138 gnd gnd 161 i/o i/o 184 i/o i/o 139 gnd gnd 162 gnd gnd 185 i/o i/o 140 v cc v cc 163 i/o i/o 186 i/o i/o 141 i/o i/o 164 i/o i/o 187 i/o i/o 142 i/o i/o 165 i/o i/o 188 i/o i/o 143 i/o i/o 166 i/o i/o 189 v cc v cc 144 i/o i/o 167 i/o i/o 190 i/o i/o 145 i/o i/o 168 i/o i/o 191 i/o i/o 146 i/o i/o 169 i/o i/o 192 i/o i/o 147 i/o i/o 170 i/o i/o 193 gnd gnd 148 ioclk, i/o ioclk, i/o 171 i/o i/o 194 i/o i/o 149 gnd gnd 172 clka, i/o clka, i/o 195 i/o i/o 150 i/o i/o 173 clkb, i/o clkb, i/o 196 dclk, i/o dclk, i/o 151 i/o i/o 174 pra, i/o pra, i/o 152 i/o i/o 175 i/o i/o 196-pin cqfp (continued) pin number a1460a function rt1460a function pin number a1460a function rt1460a function pin number a1460a function rt1460a function 48 package pin assignments (continued) 256-pin cqfp (top view) 256-pin cqfp pin #1 index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 185 186 187 188 189 190 191 192 64 63 62 61 60 59 58 57 56 8 7 6 5 4 3 2 1 49 radtolerant fpgas 256-pin cqfp pin number a14100a function rt14100a function pin number a14100a function rt14100a function pin number a14100a function rt14100a function 1 gnd gnd 45 i/o i/o 89 i/o i/o 2 sdi, i/o sdi, i/o 46 v cc v cc 90 prb, i/o prb, i/o 3 i/o i/o 47 i/o i/o 91 gnd gnd 4 i/o i/o 48 i/o i/o 92 v cc v cc 5 i/o i/o 49 i/o i/o 93 gnd gnd 6 i/o i/o 50 i/o i/o 94 v cc v cc 7 i/o i/o 51 i/o i/o 95 i/o i/o 8 i/o i/o 52 i/o i/o 96 hclk, i/o hclk, i/o 9 i/o i/o 53 i/o i/o 97 i/o i/o 10 i/o i/o 54 i/o i/o 98 i/o i/o 11 mode mode 55 i/o i/o 99 i/o i/o 12 i/o i/o 56 i/o i/o 100 i/o i/o 13 i/o i/o 57 i/o i/o 101 i/o i/o 14 i/o i/o 58 i/o i/o 102 i/o i/o 15 i/o i/o 59 gnd gnd 103 i/o i/o 16 i/o i/o 60 i/o i/o 104 i/o i/o 17 i/o i/o 61 i/o i/o 105 i/o i/o 18 i/o i/o 62 i/o i/o 106 i/o i/o 19 i/o i/o 63 i/o i/o 107 i/o i/o 20 i/o i/o 64 i/o i/o 108 i/o i/o 21 i/o i/o 65 i/o i/o 109 i/o i/o 22 i/o i/o 66 i/o i/o 110 gnd gnd 23 i/o i/o 67 i/o i/o 111 i/o i/o 24 i/o i/o 68 i/o i/o 112 i/o i/o 25 i/o i/o 69 i/o i/o 113 i/o i/o 26 i/o i/o 70 i/o i/o 114 i/o i/o 27 i/o i/o 71 i/o i/o 115 i/o i/o 28 v cc v cc 72 i/o i/o 116 i/o i/o 29 gnd gnd 73 i/o i/o 117 i/o i/o 30 v cc v cc 74 i/o i/o 118 i/o i/o 31 gnd gnd 75 i/o i/o 119 i/o i/o 32 i/o i/o 76 i/o i/o 120 i/o i/o 33 i/o i/o 77 i/o i/o 121 i/o i/o 34 i/o i/o 78 i/o i/o 122 i/o i/o 35 i/o i/o 79 i/o i/o 123 i/o i/o 36 i/o i/o 80 i/o i/o 124 iopcl, i/o iopcl, i/o 37 i/o i/o 81 i/o i/o 125 i/o i/o 38 i/o i/o 82 i/o i/o 126 i/o i/o 39 i/o i/o 83 i/o i/o 127 i/o i/o 40 i/o i/o 84 i/o i/o 128 gnd gnd 41 i/o i/o 85 i/o i/o 129 i/o i/o 42 i/o i/o 86 i/o i/o 130 i/o i/o 43 i/o i/o 87 i/o i/o 131 i/o i/o 44 i/o i/o 88 i/o i/o 132 i/o i/o 50 133 i/o i/o 175 gnd gnd 217 i/o i/o 134 i/o i/o 176 gnd gnd 218 i/o i/o 135 i/o i/o 177 i/o i/o 219 clka, i/o clka, i/o 136 i/o i/o 178 i/o i/o 220 clkb, i/o clkb, i/o 137 i/o i/o 179 i/o i/o 221 v cc v cc 138 i/o i/o 180 i/o i/o 222 gnd gnd 139 i/o i/o 181 i/o i/o 223 v cc v cc 140 i/o i/o 182 i/o i/o 224 gnd gnd 141 v cc v cc 183 i/o i/o 225 pra, i/o pra, i/o 142 i/o i/o 184 i/o i/o 226 i/o i/o 143 i/o i/o 185 i/o i/o 227 i/o i/o 144 i/o i/o 186 i/o i/o 228 i/o i/o 145 i/o i/o 187 i/o i/o 229 i/o i/o 146 i/o i/o 188 ioclk, i/o ioclk, i/o 230 i/o i/o 147 i/o i/o 189 gnd gnd 231 i/o i/o 148 i/o i/o 190 i/o i/o 232 i/o i/o 149 i/o i/o 191 i/o i/o 233 i/o i/o 150 i/o i/o 192 i/o i/o 234 i/o i/o 151 i/o i/o 193 i/o i/o 235 i/o i/o 152 i/o i/o 194 i/o i/o 236 i/o i/o 153 i/o i/o 195 i/o i/o 237 i/o i/o 154 i/o i/o 196 i/o i/o 238 i/o i/o 155 i/o i/o 197 i/o i/o 239 i/o i/o 156 i/o i/o 198 i/o i/o 240 gnd gnd 157 i/o i/o 199 i/o i/o 241 i/o i/o 158 gnd gnd 200 i/o i/o 242 i/o i/o 159 v cc v cc 201 i/o i/o 243 i/o i/o 160 gnd gnd 202 i/o i/o 244 i/o i/o 161 v cc v cc 203 i/o i/o 245 i/o i/o 162 i/o i/o 204 i/o i/o 246 i/o i/o 163 i/o i/o 205 i/o i/o 247 i/o i/o 164 i/o i/o 206 i/o i/o 248 i/o i/o 165 i/o i/o 207 i/o i/o 249 i/o i/o 166 i/o i/o 208 i/o i/o 250 i/o i/o 167 i/o i/o 209 i/o i/o 251 i/o i/o 168 i/o i/o 210 i/o i/o 252 i/o i/o 169 i/o i/o 211 i/o i/o 253 i/o i/o 170 i/o i/o 212 i/o i/o 254 i/o i/o 171 i/o i/o 213 i/o i/o 255 i/o i/o 172 i/o i/o 214 i/o i/o 256 dclk, i/o dclk, i/o 173 i/o i/o 215 i/o i/o 174 v cc v cc 216 i/o i/o 256-pin cqfp (continued) pin number a14100a function rt14100a function pin number a14100a function rt14100a function pin number a14100a function rt14100a function 51 radtolerant fpgas package mechanical drawings 84-pin cqfp (cavity up) notes: 1. seal ring and lid are connected to ground. 2. lead material is kovar with minimum 50 microinches gold plate over nickel. 3. packages are shipped unformed with the ceramic tie bar in a test carrier. d2 d1 e a1 a c h e2 e1 b l1 f lid top view side view 52 package mechanical drawings (continued) 172-pin cqfp (cavity up) notes: 1. seal ring and lid are connected to ground. 2. lead material is kovar with minimum 50 microinches gold plate over nickel. 3. packages are shipped unformed with the ceramic tie bar. a b h d1 d2 e2 e1 f l1 k ceramic tie bar no. 1 e a1 c lead kovar lid top view side view 53 radtolerant fpgas package mechanical drawings (continued) 132-pin, 196-pin, and 256-pin cqfp (cavity up) notes: 1. outside leadframe holes (from dimension h) are circular for cq256. 2. seal ring and lid are connected to ground. 3. lead material is kovar with minimum 50 microinches gold plate over nickel. 4. packages are shipped unformed with the ceramic tie bar. a b h d1 d2 e2 e1 f l1 k ceramic tie bar no. 1 e a1 c lead kovar lid top view side view 54 ceramic quad flat pack cqfp 84 cqfp 132 cqfp 172 symbol min. nom. max. min. nom. max. min. nom. max. a 0.070 0.090 0.100 0.094 0.105 0.116 0.094 0.105 0.116 a1 0.060 0.075 0.080 0.080 0.090 0.100 0.080 0.090 0.100 b 0.008 0.010 0.012 0.007 0.008 0.010 0.007 0.008 0.010 c 0.004 0.006 0.008 0.004 0.006 0.008 0.004 0.006 0.008 d1/e1 0.640 0.650 0.660 0.940 0.950 0.960 1.168 1.180 1.192 d2/e2 0.500 bsc 0.800 bsc 1.050 bsc e 0.025 bsc 0.025 bsc 0.025 bsc f 0.130 0.140 0.150 0.325 0.350 0.375 0.175 0.200 0.225 h 1.460 bsc 2.320 bsc 2.320 bsc k 2.140 bsc 2.140 bsc l1 1.595 1.600 1.615 2.485 2.500 2.505 2.485 2.495 2.505 note: 1. all dimensions are in inches except cq256, which is in millimeters. 2. bsc equals basic spacing between centers. this is a theoretical true position dimension and so has no tolerance. ceramic quad flat pack cqfp 196 cqfp 256 symbol min. nom. max. min. nom. max. a 0.094 0.105 0.116 2.28 2.67 3.06 a1 0.080 0.090 0.100 1.93 2.29 2.65 b 0.007 0.008 0.010 0.18 0.20 0.22 c 0.004 0.006 0.008 0.11 0.15 0.18 d1/e1 1.336 1.350 1.364 35.64 36.00 36.36 d2/e2 1.200 bsc 31.5 bsc e 0.025 bsc 0.50 bsc f 0.175 0.200 0.225 7.05 7.75 8.45 h 2.320 bsc 70.00 bsc k 2.140 bsc 65.90 bsc l1 2.485 2.495 2.505 74.60 75.00 75.40 note: 1. all dimensions are in inches except cq256, which is in millimeters. 2. bsc equals basic spacing between centers. this is a theoretical true position dimension and so has no tolerance. 55 radtolerant fpgas actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel europe ltd. daneshill house, lutyens close basingstoke, hampshire rg24 8ag united kingdom tel: +44-(0)125-630-5600 fax: +44-(0)125-635-5420 actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel asia-pacific exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81-(0)3-3445-7671 fax: +81-(0)3-3445-7668 5172139-3/1.00 |
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